A 5V 8b 40MSample/s pipelined analog-to-digital converter

In this paper, a 5V 8b 40Msamples/s pipelined A/D converter is presented. The A/D converter contains seven stages and each stage realizes a resolution of 1.5bit. To reduce both linear and nonlinear errors, bottom-plate sampling, bootstrap and digital correction techniques are applied in ADC design. Accurate clocks are necessary for those techniques. Experiment results are obtained, with 1MHz input signal, the ADC acquired SNDR of 48.2dB SFDR of 58.2dB and 7.8 ENOB. The chip is fabricated in 0.35 /spl mu/m N-well CMOS technology and occupies an area of 4 mm/sup 2/.