A monolithic 1 GHz 0.6/spl mu/m CMOS low jitter PLL

A low jitter 1 GHz phase locked loop (PLL) circuit for clock synchronization of high-speed data transmission systems has been realized monolithically in a native 0.6/spl mu/m CMOS technology. The implemented PLL consists of a phase detector (PD), a loop filter and a three-stage voltage-controlled ring oscillator (ring VCO). Fully differential topology is employed to suppress undesired noises and to depress clock jitter. The RMS jitter is lower than 4.8 ps at 1 GHz, the phase noise is as slender as -97 dBc/Hz at 10 kHz offset and the total power consumption is 214 mW when the PLL is locked at 1 GHz under a single 5 V supply.