A 3.125Gbit/s CMOS clock and data recovery circuit

A 3.125Gbit/s clock and data recovery (CDR) circuit is described. The circuit adopts parallel structure to recover clock from high-speed data stream. The working clock is reduced by this method and lower power is achieved. Timing jitter has been considered carefully and the loop parameters are optimized to reduce the output jitter. The circuit is designed with 0.18/spl mu/m CMOS process: the simulated function and performance meet the requirements and the core power dissipation is 56mW.