Micro-architecture optimization of THUMP105 SOC implementation

At microarchitectural level this paper presents our research on performance-constraint problems for VLSI system design with IP and VC cores. With 32bit embedded and low-power processor THUMP105 as an example, delay complexity measure of control module, and signal noise ratio (SNR) of special managing request (SMR) signals were discussed to evaluate final performance and power consumption. Optimized results of THUMP105 indicated that the critical path delay was reduced by 46.8% at same supply voltage, which means that the lower supply voltage can be employed resulting in significant power saving with same performance constraints.