Fabrication of strained Si channel PMOSFET on thin relaxed Si/sub 1-x/Ge/sub x/ virtual substrate

A novel MBE-grown method using low-temperature Si technology is introduced into the fabrication of strained Si channel PMOSFETs. By sandwiching a low-temperature Si layer between Si buffer and SiGe layer, the strain relaxation degree of the SiGe layer is increased and the threading dislocations (TDs) are hold back from propagating to the surface. As a result, the thickness of relaxed Si/sub 1-x/Ge/sub x/ epitaxy layer on bulk silicon is reduced from several micrometers to approximate 400nm (x=0.2). The DC characteristics measured by HP 4155B indicate that hole mobility has an maximum enhancement of 25% compared to similarly processed bulk Si PMOSFET.