Design of CMOS distributed amplifiers for maximum bandwidth

This article presents a new methodology for the design of CMOS distributed amplifiers to achieve the largest possible bandwidth in a specific CMOS technology. The new design employs smaller spiral inductors that not only reduce the chip area significantly but also increase the bandwidth of the amplifier. A bandwidth of 29 GHz is achieved using a four-stage DA in 0.18 /spl mu/m standard CMOS technology. The gain of the amplifier is 7 dB, the reverse coupling does not exceed -12 dB, and the maximum input and output ports reflection coefficients are -8 dB and -9 dB for terminating loads of 50 ohms, respectively.