Substrate-well modeling for DSM triple-well CMOS digital circuits with adjustable V/sub T/

A distributed model of the substrate well is developed in order to characterize the performance of CMOS standard-cell circuits with adjustable V/sub T/ implemented in a triple-well process. This model is used to study the impact of the number of gates placed in the same well on performance and to draw conclusions for optimal design. A lumped equivalent network of the well is derived as a function of the number of gates in the well. The impact of the well contact placement and the resistance between the well contacts and the bulk of the transistors is analyzed for standard-cells on logic circuits.