Stacked 3-D Fin-CMOS technology

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture.