High-performance arithmetic coding VLSI macro for the H.264 video compression standard

This work investigates the algorithmic complexity of arithmetic coding in the new H.264 video coding standard and proposes a coprocessor to reduce it by more than an order of magnitude. The coprocessor is based on an innovative algorithm named the MZ-coder and maintains the original coding efficiency with a multiplication-free, non-stalling, fully pipelined architecture with modest hardware requirements. The coprocessor delivers a constant throughput for both coding and decoding of 1 bit per cycle and can be attached to a controlling CPU whose ISA has been extended with arithmetic coding instructions.