An IPv6 enabled packet engine design for home/SOHO routers

Due to the diversity of Internet applications and services, traditional software-based networking devices may not be sufficient to afford the processing load imposed by the services. One example is the mixed-version IP environment in which routers must handle the IPv4/IPv6 translation while keeping the IP processing at the line speed. In this paper, we present our work for the design of a protocol optimized packet processing engine that provides common IP services and mixed version translation. This silicon is written in VHDL and is tested in a Xilinx Vertex II FPGA development board.