A fractional-n PLL frequency synthesizer design

This paper proposes a fractional-N phase-locked loop (PLL) frequency synthesizer using 3rd order /spl Delta//spl Sigma/ modulator for 915 MHz medium speed FSK wireless link. The voltage-controlled oscillator (VCO), pre-scaler of divide-by-8, phase frequency detector (PFD), and charge pump (CP) have been developed with 0.25-/spl mu/m CMOS process. A 3rd order external loop filter has been optimized to reduce the lock-in time. The fractional-N divider and 3rd order /spl Delta//spl Sigma/ modulator have been designed with the VHDL codes, and implemented through the FPGA board of the Xilinx Spartan2E. The VCO has been designed to span from 900 MHz to 950 MHz band using LC resonator, and a fractional-N divider uses a 36/37 modulus and 3rd order /spl Delta//spl Sigma/ modulator to reduce the fractional spur. The measured result shows that the RF output power of the frequency synthesizer is -10 dBm, the phase noise is -78 dBc/Hz at 100 KHz offset frequency, the minimum frequency step is 10 kHz, and the maximum lock-in time is around 800 ms with 10 MHz step change.