Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques [CMOS transistors]

A very efficient trapping has already been reported on transistors with Hf-based gate oxides. The authors have attributed these phenomena to the presence of electron traps at the HfO/sub 2//SiO/sub 2/, interface or in the HfO/sub 2/ bulk. More recent experimental results show that the trapping occurs in the bulk of the high-k dielectrics rather than at the high-k/SiO/sub 2/ interface. In this work, we apply an improved pulsed gate voltage technique for the electrical analysis of the transient charge trapping and detrapping effects, and based on the observed trapping and detrapping kinetics, we develop a new approach in order to characterize the energy distribution of the responsible HfO/sub 2/ traps.