Fast wafer level data acquisition for reliability characterization of sub-100 nm CMOS technologies

The application of fast measurement techniques for the reliability assessment of sub-100 nm CMOS technologies was recently proposed in the literature. To realize fast wafer level current measurements, ranging from nA to mA, a measurement setup was developed consisting of an analog input/output PCI card and (log-lin) current-voltage converters. With this setup, a measurement time resolution of /spl sim/20 /spl mu/s was achieved, which is significantly faster than the conventional source measurement unit (SMU) based measurements via GPIB control. The setup was verified using time dependent dielectric breakdown measurements (of n-MOSFETs) on SiON gate dielectrics and charge trapping measurements in HfO/sub 2/ layers.