Reconfigurable address generators for stream-based computation implemented on FPGAs

This paper describes the design and implementation of an address generator for stream-based computation. The unit can generate addresses by a 1, 2 or 3-dimensional mapping from a linear data string in memory. A processing unit will get the required data in a continuous stream without empty time slots, even when switching between addressing algorithms. Each algorithm is specified by a set of parameters loaded into FIFOs in background. The unit is specified by VHDL, simulated, synthesized and implemented on an FPGA of type Xilinx Virtex-II Pro. A speed of 144 MHz is obtained for generating 36 bit addresses. Ideas for expanding the flexibility of the unit are discussed.