Transient-induced latchup in CMOS technology: physical mechanism and device simulation

The physical mechanism of transient-induced latchup (TLU) in CMOS ICs has been clearly characterized by device simulation and experimental verification in time domain perspective. An underdamped sine-wave-like voltage has been clarified as the real TLU-triggering stimulus under system-level electrostatic discharge (ESD) test. The specific "sweep-back" current caused by the minority carriers stored within the pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU.