Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate

In this work, HfSiON gate dielectric is integrated for the first time in dual gate oxide of DRAM with recess channel arrary transistor (RCAT) and W/poly-Si gate for the development of sub-60nm DRAM technology. No degradation of cell transistor characteristics was observed with HfSiON gate dielectric. In peripheral transistors, excellent sub-threshold swings and driving current of 515 /spl mu/A//spl mu/m and 216 /spl mu/A//spl mu/m for nMOS and pMOS, respectively, at V/sub dd/=1.8V and I/sub off/=20/spl mu/A//spl mu/m were obtained. Compared to surface channel pMOSFET, lower V/sub th/ was achieved in buried channel pMOSFET due to fermi-level pinning. Negligible increase of gate leakage current during post annealing up to 950/spl deg/C for 30min is shown the excellent thermal stability of HfSiON dielectric.