Package-strain-enhanced device and circuit performance

The hole mobility enhancement can be as high as /spl sim/18% for SiO/sub 2/ and /spl sim/20% for high-k HfO/sub 2/ gate stack dielectrics with the uniaxial compressive strain (0.2%) parallel to the channel. The highest drain current of /spl sim/22% at saturation and /spl sim/30% at linear region is observed for the bulk Si PMOS with high-k gate stacks. The drain current and hole mobility of bulk Si PMOS are degraded under the small biaxial tensile strain, while substrate-strained Si device displays the opposite. The nonoptimized ring oscillator has the speed enhancement of /spl sim/7% under the uniaxial tensile strain parallel to NMOS channel. Proper package strain also gives the drive-current as well as mobility enhancement at 100/spl deg/C.