Negative bias temperature instabilities in HfSiON/TaN-based pMOSFETs

Negative bias temperature instabilities (NBTI) in devices with SiO/sub x//HfSiON stacks and TaN gates is reported, for different SiO/sub 2//HfO/sub 2/ compositions, for stacks with same physical thickness (t/sub phys/) and same equivalent oxide thickness (EOT). It is shown that V/sub th/ shifts increase with time like power laws, /spl Delta/V/sub th/=At/sup /spl alpha//, like in SiO/sub 2/ and SiON-based devices. When comparing AV/sub th/ shifts for same t/sub phys/, it is found that NBTI increases with increased HfO/sub 2/ content. On the other hand, comparison of V/sub th/ shifts for devices with comparable EOT indicates that an optimal HfO/sub 2/ content, around 53%, results in minimal NBTI. These results can be qualitatively explained by the reaction-diffusion model. The power law exponent /spl alpha/ is shown to decrease with increasing amount of HfO/sub 2/. This finding has an important impact on the extrapolation of the device lifetime at operating conditions, which is found to be similar for layers with HfO/sub 2/ compositions in the range 53-100 %.