On-chip cache algorithm design for multimedia SOC

In order to optimally implement real time, high throughput, data intensive multimedia applications, it is crucial to optimize the performance of the memory subsystem to minimize excessive off-chip memory bandwidth subject to the constraint of available on-chip memory cache size. This can be accomplished by customizing algorithm transformation and designing a customized cache address mapping algorithm for a specific class of multimedia applications. In this paper, we propose an algorithm transformation and customized cache mapping to improve the data reusability and reduce address conflict which in turn, reduces the cache miss and memory I/O bandwidth for the block-based full-search motion estimation algorithm. Simulation results using test video sequences demonstrate marked performance improvement.