Serial semi floating gate MOS D/A converter with configurable resolution

In this paper we present a new proposal for implementing a voltage mode multiple valued (MV) digital to analog (D/A) converter. The circuit has been implemented using experimental recharged semi floating-gate (SFG) technique for conventional CMOS processes. Simulated results are obtained using Cadence Spectre with AMS 0.35 /spl mu/ process parameters and 2 V supply voltage. For performance evaluation and error estimation the results from Spectre is compared to a theoretical Matlab model. The circuit is suitable for low power design, V/sub dd/ <2 volt. It has configurable resolution, which allows the output symbol length (n) or MVL radix (2/sup n/) to be selected after fabrication and design optimization. The design is a binary weighted D/A converter structure for serial binary input with low resolution.