Modeling and simulation of phase-locked loop with Verilog-A description for top-down design

In this work, we describe modeling and simulation methodologies by Verilog-A of the phase-locked loop (PLL). We model the affects by the variation of the power supply voltage to component circuits in the PLL. Then, we describe this effect by Verilog-A. The behavior of the circuit model described by Verilog-A is verified and the validity of this modeling is shown by the comparison with simulation results by HSPICE. Finally, it is shown that the application of Verilog-A is useful and practical in the design of analog-digital mixed-signal circuits.