A high-speed divide-by-32/33 frequency divider in 0.25/spl mu/m CMOS technology

A high-speed divide-by-32/33 frequency divider has been developed in a 0.25/spl mu/m CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed divider can operate at high frequency with a low-power consumption. Based on the 2.5V 0.25/spl mu/m CMOS model, simulation results indicate that the maximum input frequency of the divider is up to 3.2GHz. Running at a power supply of 2.5V, the circuit consumes only 4.6mA at input frequency of 2.5GHz.