A 0.35 /spl mu/m low-noise adaptive pad driver for high-speed optical wireless receivers

This paper addresses the design of a high-speed low-noise pad driver for optical wireless communication receiver applications. This pad driver operates at bit rates of up to 310 Mb/s, has enough driving capability to drive a range of high loading capacitive output pads (0.5 pF - 20 pF) and produces a rail-to-rail output voltage while improving immunity to noise from interconnects and package parasitics. Simulations on the pad driver circuit using 0.35 /spl mu/m CMOS technology are provided, confirming the accuracy of expected performance such as low power dissipation, low power/ground bounce, and low output ringing.