High PSRR CMOS voltage reference for negative LDOS

This work presents a CMOS voltage reference built within a negative LDO processed in a double-metal 0.8 /spl mu/m CMOS technology. The reference consumes 12 /spl mu/A, and delivers a stable output voltage of -1.2 V. Power supply rejection ratio is 86 dB at low frequencies, while TC is within /spl plusmn/50 ppm//spl deg/C, and un-trimmed V/sub REF/ spread 60 mV (/spl plusmn/3/spl sigma/).