A new FGMOS active resistor with improved linearity and frequency response

A new linearity improvement technique for a CMOS active resistor is presented. In order to minimize the silicon area, an original method based on the utilization of FGMOS (floating gate MOS) transistors and on an optimal implementation of the current-controlled voltage generators from the active resistor circuit is designed, having the result of about two order of magnitude reducing area with respect to a classical resistor. A new idea for minimizing the errors introduced by the second-order effects is further presented. The circuit estimated linearity error is under 1% for an extended input range. The active resistor is designed for low-voltage low-power application and it is implemented in 0.35 /spl mu/m CMOS technology.