CMOS design of a multibit bandpass continuous-time sigma delta modulator running at 1.2 GHz

This paper presents the design technique for a high speed sixth order bandpass continuous-time sigma-delta modulator in a standard 0.35/spl mu/m CMOS technology. Three resonators are implemented in a parallel structure using highly linear operational transconductance amplifiers (OTA). Furthermore, an improved method employing two 3-bit flash converters as a loop quantizer allows doubling the sampling frequency. As a consequence we can design a modulator clocked at 1.2GHz allowing the integration of passive LC-filters in this standard technology. Transistor level simulations show that the modulator can achieve a signal-to-noise and distortion-ratio (SNDR) of 98dD over a 2MHz signal band at 300MHz central frequency.