T-Rex, a blade packaging architecture for mainframe servers

In this paper, we describe the application of the blade packaging concept to the IBM zSeries eServer z990, code-named T-Rex. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of buses required to support a processing operating frequency of 1.25 GHz in a symmetric multiprocessing (SMP) architecture with up to 64 processor cores are tabulated. The evolution of the I/O circuits for each of these buses is described along with the bus cycle time and bandwidth trends