An efficient software-based implementation of a joint-detection/spatial processing receiver for TD-SCDMA

TD-SCDMA is known as the low chip-rate time division duplex (LCR TDD) mode of the third generation partnership program (3GPP). It incorporates a combination of time and code division multiple access schemes and is well suited for advanced techniques like joint detection (JD) and spatial processing. This work focuses on the performance and memory requirements of a completely software-based zero-forcing block linear (ZF-BLE) JD and spatial processing receiver for a TD-SCDMA system, which combats intersymbol interference (ISI) as well as multi access interference (MAI). The analysis is based on the TMS320C6416T, which is a 1 GHz DSP with four 16-bit MAC units and a 1 Mbyte level-2 unified on-chip memory space.