IEEE P1500-compliant test wrapper design for hierarchical cores

Most system-on-chips (SOCs) today contain hierarchical cores that have multiple levels of design hierarchy. An efficient wrapper design for hierarchical cores is necessary to facilitate modular testing of SOCs. In most of the prior work on wrapper design for embedded cores, all the cores are assumed to have a flattened hierarchy. In this paper, we present a hierarchical core model and a generic IEEE P1500-compliant wrapper architecture for hierarchical cores. We assume that the embedded cores within the hierarchical cores are hard cores, since they are wrapped by the core vendor a priori and they have their own TAM architecture. Unlike prior wrapper design methods that assume a single test mode for hierarchical core wrappers, we present a general architecture for hierarchical core wrappers and describe various modes of operation of the wrapper. We design reconfigurable wrappers for hierarchical cores that can operate efficiently in all the test modes, thereby minimizing the overall time required to test the hierarchical core for any given TAM width. We propose a heuristic approach to solve the problem of hierarchical core wrapper design, and present experimental results for two hierarchical cores present in an ITC'02 benchmark SOC.