A floating gate single electron memory device with Al/sub 2/O/sub 3/ tunnel barriers

The emerging research devices section of the 2003 edition of the semiconductor industry roadmap (ITRS 2003) lists single electron memories as one possible family of devices with the potential to continue the historical scaling trends in the density and performance of semiconductor memories. Furthermore, the ITRS 2003 roadmap calls attention to the introduction of high K gate dielectrics in DRAM's and their future integration into flash memory process. In light of this, a study of the behavior of single electron memory devices utilizing high K dielectrics is essential to clearly understand the potential of these devices in extending the roadmap. In the aluminum tunnel junction based single electron memory cell (K.K. Yadavalli et al., J. Vac. Sci. B vol. 21, 2860, 2003), the memory node is an aluminum floating gate closely coupled with the single electron transistor used as a readout device. We have developed a process for the fabrication of Al/sub 2/O/sub 3/ tunnel junctions with precise physical and electrical properties using plasma oxidation of aluminum.