Influence of Al/sub 2/O/sub 3/ dielectrics on the trap-depth profiles in MOS devices investigated by the charge-pumping method

High dielectric constant materials come into focus as a replacement for the currently used silicon-dioxide or silicon-oxynitride dielectrics in CMOS processes due to further densification of devices. One main issue of these alternative materials is charge trapping in the dielectric. Charge trapping causes instabilities of electrical properties like threshold voltage shifts and less reliability. Thus, trapping behavior of alternative dielectric materials is an important question. Within this paper trap density depth profiling based on charge-pumping measurements were applied to Al/sub 2/O/sub 3/ high-k dielectric transistors. With this method it was possible to analyze the depth of trap centers throughout the dielectric. A homogenous distribution of trapping centers was observed. The trap-density was lower for a SiO/sub 2/ interface layer compared to a Si/sub 3/N/sub 4/ interface. However, in general, the density was four orders of magnitude higher with an Al/sub 2/O/sub 3/ dielectric compared to standard gate-oxide. Device stability can be correlated to trap densities and resulting threshold voltage shifts. Furthermore, analytical results give strong indications that silicon interdiffusion and grain boundaries are the main cause for trap sites.