Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic

This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable/disable CMOS differential logic (MOECDL) style. The MOECDL structure proposed represents a promising technique for iterative networks and self-timed circuits. The recursive property of CLA algorithm has been efficiently exploited to demonstrate the advantages of multiple-output structures. The 32-bit MOECDL CLA circuit has been designed into a standard 0.5 /spl mu/m CMOS technology. Comparison to the known DCVS style is presented through electrical simulation.