A 16b 65 MSps pipeline ADC core with 230 fs clock jitter in 3.3 V SiGe BiCMOS: from simulation to silicon

This work introduces key simulation techniques enabling the design of a 16b 65 MSps pipeline ADC in 0.4 /spl mu/m, 45 GHz-f/sub T/ SiGe BiCMOS. A complete methodology for INL investigation with SPICE leads to understand the distortion introduced by Track/Hold as well as quantizer at 3.3 V supply and high input range (4Vpp). Simulations of aperture uncertainty are presented that match the measured 230 fs jitter, yielding 74.5 dBFS SNR at 150 MHz input. The test chip delivers 78.3 dBFS SNR, 88 dBc SFDR at 65 MSps/1 MHz with 970 mW power consumption.