Power-aware pipelining design of an 8-bit CLA using PLA-styled all-N-transistor logic

A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks, which are arranged in a PLA design style with power-aware pipelining is present. The pull-up charging and pull-down dis-charging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The analysis of the area (transistor count) tradeoff is also presented in this paper. The output of the addition of two 8-bit binary numbers is done in 2 cycles. The proposed power-aware pipelining design methodology takes advantage of shutting down the processing stages with identical inputs in two consecutive cycles. Not only is it proved to be also suitable for the long adders, the power consumption is drastically reduced by at most 50% at every process corner.