A novel evolutionary algorithm for analog VLSI layout placement design

In this paper, we present a novel macro-cell placement scheme following the optimization flow of a hybrid genetic algorithm (GA) controlled by the methodology of simulated annealing. It employs a two-dimensional bit-matrix representation and flexible operators. The dedicated cost function covers the special requirements of analog integrated circuits, including area, net length, aspect ratio, proximity, symmetry constraints, parasitic effect, etc. To study the algorithm parameters, the fractional factorial experiment using an orthogonal array has been employed, followed by a meta-GA to determine the exact parameter values. The proposed algorithm has been tested using several analog circuits, and appears superior to the simulated-annealing approaches mostly used for analog macro-cell placement.