Technology portable delay model for DSM CMOS inverters

A closed form expression to accurately estimate the delay of a CMOS deep submicron (DSM) inverter is presented in this paper. This model does not depend on any extracted or fitting parameters. Instead it depends on the device model parameters. This model exhibits a good accuracy when compared with Spectre simulations using BSIM3v3 model, for a wide range of device sizes, capacitive loads, transition times, and aspect ratios (W/sub p//W/sub n/). Since this model is independent of extracted and fitting parameters, it is technology portable. The model is validated for three DSM technologies (UMC's 0.13 /spl mu/m, and TSMC's 0.18 /spl mu/m and 0.25 /spl mu/m). For all, the model shows good accuracy with on average error of about 4%. The maximum error is less than 10%.