Low leakage circuit design for FPGAs

Reconfigurable computing is well suited for wireless applications because of its capability to adapt to changing communication protocols. However, as technology scales, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents different buffered switches mixing low and high threshold transistors which trade some delay performance to reduce by two orders of magnitude the leakage current of the switch blocks which generate most of the dissipation in FPGAs.