Sequential synthesizable embedded programmable logic cores for system-on-chip

Previous work has suggested that "soft" synthesizable programmable logic cores can efficiently provide small amounts of post-fabrication flexibility to integrated circuits. Previous architectures restrict the circuitry assigned to the core to be combinational. We present two methods to enhance these architectures to support sequential logic. We apply these methods to a previously developed fabric, and optimize and compare them. We also describe a proof-of-concept chip employing one of our techniques.