Back-gated SOI technology: power-adaptive logic and non-volatile memory using identical processing

A back-gated scalable silicon-on-insulator (SOI) technology that provides a non-volatile memory, logic with adaptive power-performance trade-off and buried interconnectivity is reported. The back-gate approach has the following characteristics: (1) a logic transistor whose threshold voltage modulation allows adaptive power control of digital and analog circuits, (2) a non-volatile memory where the read-transistor scaling is decoupled from storage constraints, (3) good SOI thickness control, (4) speed degradation due to alignment tolerances lower than 16%, (5) a new analog design approach to achieve adaptive low voltage operation within digital constraints.