Investigations on possible occurrence of ballistic transport in different NMOS architectures

This paper examines the performance of different NMOS devices (strained and unstrained bulk silicon, undoped single gate and double gate strained or unstrained SOI or SON devices) in the full ballistic regime of transport. The realism of this full ballistic transport assumption is also discussed, showing that even considering the most challenging structures, full ballistic transport will probably not be reached until channel length is lower than 10 nm.