Successful integration of an ultra low thermal budget process solution based on solid phase epitaxy for sub-50nm CMOS technologies

We demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, it is shown that the use of self-amorphizing implants for the source/drain (S/D) leads to a good transistor performance without significantly deteriorating the diode leakage. Moreover, it is proved that specific attention must be paid to salicidation with an ultra low thermal budget. Since the highest temperature used after gate definition is 700/spl deg/C, this process is perfectly suitable for the integration of temperature sensitive modules such as high-k dielectrics, metal gates or strained channels.