RM/sup 3/ integration of InP based 1.55 /spl mu/m P-i-N photodetectors with silicon CMOS optical clock distribution circuits

Recess mounting with monolithic metallization, or RM/sup 3/ integration, is being developed to integrate III-V photodiodes on silicon CMOS circuits for optical clock distribution applications. In RM/sup 3/ integration, partially processed heterostructure devices are placed in recesses formed in the dielectric layers covering the surface of an integrated circuit chip, the surface is planarized, and monolithic processing is continued to transform the heterostructures into optoelectronic devices monolithically integrated with the underlying circuitry.