A methodology for performance driven incremental placement with high level exploration

In order to accurately evaluate a design decision made during high level synthesis (HLS), it is essential to clearly account for its effects on the final layout. We propose a mixed integer linear programming (MILP) based approach to perform incremental global placement driven by delay budgeting in a HLS framework. The methodology incrementally updates global placement to accommodate design decisions made during HLS. Given a target clock speed, a delay budget is associated with interconnects that change during exploration. The placer aims at accommodating changes in the RTL netlist while meeting design constraints. Integration of this strategy during HLS design space exploration allow the designer to examine various RTL structures for better post-layout physical characteristics. Experiments show that the approach is extremely fast and yields compact placement results for accommodating HLS design decisions.