14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC

A high performance sample-and-hold (S/H) circuit intended a fast pipelined analog to digital converter was designed and implemented using a 0.18 /spl mu/m CMOS process, the sampling rate of the proposed S/H module is 50 MS/s with a bandwidth of 20 MHz and a power supply of 1.8 V. Using switched capacitor differential topology, double bootstrapped switches and several native transistors, we optimized with VerilogA models the amplifier and the switches to end up with the optimized high performance circuit. The post layout simulation allowed to reach an SFDR of 88.6 dB for 20 MHz input signal. The circuit was integrated to other building blocks to construct a pipelined ADC which is now under fabrication.