A subtraction-based adder amplifier for 10b 50 MS/s low-power pipelined-ADC's

We propose a subtraction-based adder amplifier to be used to implement high-speed and low-power pipelined-ADC's which are employed for high-speed signal processing, i.e. image processing. Proposed amplifier, to be used as a residue amplifier, consumes low-power and occupies small area. We analyzed the amplifier and designed a 1-bit stage of a 10b 50 MS/s pipelined analog-to-digital converter.