In-line defect reduction from a historical perspective and its implications for future integrated circuit manufacturing

The enormous progress in integrated circuit manufacturing over the last 30 years would have been impossible without the science of yield enhancement and defect reduction. This paper traces the evolution of this science, reviewing the history of defect inspection tooling, the practices developed for finding root causes of defects, yield modeling techniques, and important defectivity issues for current generation copper and low-K dielectric metallization. Based on the historical perspective and current status of yield enhancement technology, the paper anticipates future developments required to extend yield learning to sub-0.1-/spl mu/m technology generations.