A VLSI architecture of G.SHDSL transceiver

This paper presents a design of transceiver architecture specifically for SHDSL system. It integrates programmable karner, trellis encodeddecoder, PSD filter and two adaptive filters of Echo Cancellation (EC) and DFE equalizer (EQ) at the receiver. We propose a method, filtered-X algorithm, to solve the joint EQ and EC adaptation issue with reasonable complexity. Moreover an alldigital timing recovery is adopted in receiver to compensate the clock offset. Fixed-point simulations of the whole system show the proposed architecture is capable for SHDSL system.