Three-dimensional round-robin scheduler for advanced input queuing switches

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair access in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output. In an N /spl times/ N switch, our scheduler determines which queue in the total M /spl times/ N input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines M /spl times/ K queues in every K (M) cycle when K >= M (K <= M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The proposed round-robin scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.