A 10 b, 40 Msample/s, 25 mW pipeline analog to digital converter

This paper describes a 10 b pipelined ADC designed in 0.35 /spl mu/m CMOS technology which achieves a power dissipation of 25 mW at full speed operation from a single 3 V supply. The proposed high speed gain-boosted operational amplifier make it possible to achieve requirements of 10-bit resolution and settling time of 8 ns within 0.01% accuracy. A dynamic comparator is used for power efficiency. This design achieves INL and DNL of 0.68 LSB and 0.45 LSB respectively, while SNDR is 58.2 dB and SFDR is 73.4.