Design of circuits for a robust clocking scheme

The design of a clock distribution network in a digital integrated circuit is challenging in terms of obtaining low power consumption, low waveform degradation, low clock skew and low simultaneous switching noise. In this work we aim at alleviating these design restrictions by using a clock buffer with reduced size and a D flip-flop circuit with relaxed constraints on the rise and fall times of the clock. According to simulations the energy dissipation of a D flip-flop, implemented in a 0.35 /spl mu/m process, increases with only 21% when the fall time of the clock is increased from 0.05 ns to 7.0 ns. Considering that smaller clock buffers can be used there is a potential of power savings by using the suggested clocking scheme.